In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a CDR system, timing information is extracted from an input data stream and a recovered clock signal of a given frequency is generated, often with a number of additional phase-offset clock signals having the same frequency but with different phases than the recovered clock signal.
FIG. 1 illustrates the transitions of a data stream histogram 100 for a given unit interval (UI). As shown in FIG. 1, the input data stream is “ideally” sampled at a sample point 110-n substantially in the middle of the unit interval between two adjacent transition points 120-n, 120-n+1. The phases of the phase-offset clock signals generated by the CDR system are often adjusted to align with the transition points 120-n, 120-n+1 and sample point 110-n. Thus, the phase of a sampling clock is often adjusted so that the data sampling is performed at the sample point 110-n, substantially at the center of a “data eye,” in a known manner. In addition, the phase of a transition clock is often adjusted so that additional sampling is performed at the transition points 120-n, 120-n+1, to maintain proper timing and thereby determine an appropriate location of the sample point 110-n. 
The duty cycle of a clock signal can be expressed as the ratio of all pulse durations to the total period. A clock signal is a square wave that should typically demonstrate a 50% duty cycle. Duty cycle distortion arises, for example, due to mismatches in the clock buffers that are required to drive these clock phases, and due to variations in the different signal paths for clock and data. The target 50% duty cycle feature is particularly important for high-speed applications where both positive and negative edges of the clock signal are often used to sample the incoming signal. Thus, a trimming technique is often performed for the clock buffers to adjust a phase of the corresponding clock signal and thereby compensate for the mismatch.
A number of techniques have been proposed for the trimming of clock buffers. Existing techniques, however, often use a reference clock to trim the different clock signals. Any duty cycle distortion in the reference clock directly and negatively influences the performance of the clock trim operation. A need therefore exists for improved techniques for the trimming of clock buffers that demonstrate a reduced sensitivity to duty cycle distortion in the reference clock.